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Modular Dual VC Envelope Generator
quad VCO
dual VCF
dual VCA
power supply
This envelope generator was the first thing which came into my mind when I decided to make a nice modular synth, but it took me more than I expected to finish it. I couldn't resist to make it 5 stages, bipolar and voltage controlled. ADDSR stands for Attack, Decay 1, Decay 2, Sustain, Release. Maybe I should name it ADBDSR (decay-break-decay). Originally it ought to have voltage controlled "punch" (transition from linear to log slope) in attack and 1st decay stage. Unfortunately nonlinearities in control paths (don't ask) killed this idea. It is completely tested, working circuit, but I may introduce some changes later.
Any comments are appreciated.
  • See the photo of the prototype board (many changes since original project)
  • Look how it is tested
  • And here you can find few examples of what it can do

0.5ms - 50s
anywhere within -5V to +5V range with no respect to each other
Control voltages:
-5V..+5V for levels and times
Rest offset voltage:
less than 10mV for most of the settings. Getting worse with at release time setting
Power supply:
+/- 9V.
Board dimensions:

see the back of it,
and the back without the boards

Schematic and techtalk

Click on the image to see large, readable schematic
The picture shows simplified schematic of VCADDSR using 1/4 of SSM2164 quad VCA chip. Other 3 may be used as modulation VCAs for 3 selected parameters. There are 2 spare opamps in TL074 used for inverted envelope and sustain level cancelled one. Level control voltages relate directly to envelope levels. Increasing control voltage for time parameter decreases time (then maybe it should be called "rate" instead of "time"). It may look like overdesigned circuit, but it's not so many ICs after all. It is really simple. No tricks, straightforward design (I think). VCA core with integrator controlled by multiplexed control voltages. The integrator works with 3V signals and the rest works with 5V signals. This is to keep EG's +/-5V range and +/-9V power supply (18V for CMOS logic). Also every parameter may be modulated by VCAs with outputs at virtual ground (at opamps' summing nodes) - that's why so many inverters. Let's follow each envelope stage:
  1. Attack GATE goes high. D-flops get reset. Gates U6A&B generate address 01 for analog mux which routes attack level voltage as base voltage for integrator, and "attack time" control voltage (via inverting amplifier U8B) to VCA control input. Base voltage is always greater (with respect to GND) than applied control voltage - that's why U7B. Normally "lin att" switch is open and the difference is small, hence we get log attack slope. When "lin att" is closed, the voltage applied to integrator is 2.5 times greater than attack peek level and it works in almost linear region of exp. charging curve. The result is "linear" attack slope. The same could be done to first decay. The integrator is charging C7. When output voltage reaches attack level (note that voltages at comparator inputs are inverted and attenuated by ratio 5:3), the comparator U2B toggles (R26 and R30 give little hysteresis) and sets U4A D-flop. Those circuits between comparators and D-flops make trigger pulse every time comparator toggles.
  2. First decay. So now we have U4A set, and the mux address is 00. Decay peek (or break) voltage is applied as base, and "decay time" as VCA control. When integrator voltage reaches decay level, second comparator (U2A) toggles. Possible toggles of attack comparator don't matter, because U4A is already set, and decay comparator toggles could not have any effect before attack stage finished (D input of U4B was 0). The mux address gets to 10.
  3. Second decay and sustain With mux address 10 integrator discharges to sustain level with rate set by "sustain time" control voltage (I use the name "sustain time" for "second decay time" - I know it is misleading). Now the base voltage is routed directly (via inverter, but still..) to integrator and it discharges to sustain level exponentially. Nothing else changes while GATE is on.
  4. Release GATE goes low. Logic generates address 11 for mux, and integrator discharges to 0V with rate set by "release time" control. Release time is selected every time GATE goes low, no matter in what stage EG was at the time.

Most important parts
I used 1/4 of SSM2164 with intention to use other 3 as modulation VCAs. It could be any other OTA or discrete VCA. Beware of offset voltage though...
4011 gate, 4013 D-flop, 4052 dual mux - powered from 18V (!)
TL074; any opamp will do, only integrator should be low input bias current.
R25 sets envelope time boundaries
R20 sets envelope time range
R7 set decay slope curve; use smaller for more linear and bigger for more log
(R14=R3=R5=R1=R11) =5/3* (R35=R4=R6=R2=R12) unless linear attack is not needed - then all those resistors must be equal.
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© 2004 Roman Sowa
Last revised September 25, 2004